1. Field of the Invention
The present invention relates to an automatic rhythm generation in an electronic musical instrument. More specifically, the present invention relates to an automatic rhythm generating method and apparatus in an electronic musical instrument for automatically generating a rhythm signal responsive to rhythm information stored in a storage of a relatively decreased storage capacity.
2. Description of the Prior Art
An automatic accompaniment generation of a rhythm for adaptation to a piece of music by way of a repetition of a rhythm pattern unit responsive to rhythm pattern information selected among several kinds of rhythm pattern information stored in a storage has been proposed, such as in an electronic musical instrument, for the purpose of allowing for simultaneous performance of a music by a performer.
FIG. 1 shows a block diagram of a typical prior art automatic rhythm generator in an electronic musical instrument in which the present invention can be advantageously employed. Referring to FIG. 1, a memory 11 of such as a read only memory for storing rhythm pattern information of different rhythm pattern units is provided, which comprises a plurality of addresses, which are adapted to store various kinds of rhythm pattern units, with a predetermined plurality of addresses, say 48 addresses, being allotted for storing one kind of rhythm pattern unit. The read only memory 11 is operatively coupled to an address counter 12, such that the read only memory 11 is supplied with addressing information for selectively generating a desired rhythm by way of a repetition of a rhythm pattern unit. The address counter 12 is operatively coupled to a rhythm selecting circuit 13, such that the data representing a head address of each kind of rhythm pattern unit as selected by the rhythm selecting circuit 13 is applied to the address counter 12. The address counter 12 is further connected to receive, as a reset signal, through an OR gate 144, a rise differentiated output of a differentiation circuit 143 including a capacitor and a resistor obtainable responsive to the output of a flip-flop 142 of a toggle type or a T type, the storing state of which is reversed upon depression of a start stop command switch 141. The address counter 12 is further supplied with, as a step command signal, the output pulse of a clock generator 151 which is adapted to generate a reference clock signal. The output pulse of the clock generator 151 is also applied to a frequency divider 152, which is adapted to frequency divide the output pulse of the clock generator 151 to the number of addresses, say 48, adapted for storing one kind of rhythm pattern unit, and the output of the frequency divider 152 is also applied, as a head address command signal, i.e. a repetition command signal, to the address counter 12 through the OR gate 144. The clock generator 51 is connected to receive, as a clock generation command signal, the output of the toggle type flip-flop 142. Preferably, in order to adjust a tempo of a selected rhythm pattern, a tempo adjusting variable resistor 153 is operatively coupled to the clock generator 151, so that the oscillation frequency of the clock generator 151 can be varied through adjustment of the variable resistor 153.
Each address of the read only memory 11 comprises a predetermined plurality of bits, say eight bits, with one bit as vacant when seven kinds of musical instruments are intended, with each bit being allotted to a predetermined kind of a musical instrument. The bit outputs of a selected address of the read only memory 11 are applied, in a bit parallel fashion, to corresponding AND gates 161 to 167 at one input of each of the AND gates. The AND gates 161 to 167 are also connected to receive, at the other input of each thereof, the output pulse of the clock generator 151. If and when the logic one has been stored in any one of bits of a selected address of the read only memory 11 as addressed by the address counter 12, then the corresponding one of the AND gates 161 to 167 comes to provide the high level output at the timing of the clock pulse, which is then applied to a corresponding one of tone generators 171 to 177. Each of the tone generators 171 to 177 has been adapted to generate a tone signal of the waveform corresponding to a sound of a musical instrument being determined by each corresponding bit of the selected address of the read only memory 11. The outputs of the respective tone generators 171 to 177 are mixed and the level of the mixed output is adjusted by a volume adjusting variable resistor 181. The mixed output thus obtained is amplified by an amplifier 182 and is applied to a speaker 183. The tone generators 171 to 177, the variable resistor 181, the amplifier 182 and the speaker 183 constitute a tone generating means. As the address counter 12 counts repetitively the predetermined number of output pulses of the clock generator 151, a mixed rhythm of various musical instruments is generated by way of a repetition of selected rhythm pattern units.
FIG. 2A is an illustration showing musical characters of a samba rhythm by way of an example of a rhythm pattern unit, wherein the samba rhythm is shown by the musical characters for performance by four kinds of musical instruments, i.e. maracas, cymbal, high-bongo and low-bongo. As seen from the illustration, the samba rhythm can be represented as a rhythm pattern including a repetition of a rhythm pattern unit as shown by the musical characters in two measures.
FIG. 2B is an illustration of the musical characters for a slow rock rhythm by way of another example of rhythm pattern unit, wherein the musical characters for performance of the slow rock rhythm by three kinds of musical instruments, i.e. high-hat cymbals, snare drum and bass drum are shown. As seen from the illustration, the slow rock rhythm pattern can be represented by a repetition of a rhythm pattern unit as shown by the musical characters in two measures as shown.
In order to store the rhythm pattern information of various kinds of the rhythms in the above described read only memory 11, a scheme was employed conventionally for generating a shortest note element common to the various kinds of the rhythm pattern units, for example one note of a group of three notes of a three-divided eighth note, by allotting the number of six addresses to a quarter note, so that a samba rhythm in two measures was stored in forty-eight addresses for a four-quarter measure, for example. Table 1 shows a truth table of the data for storing the samba rhythm as shown in FIG. 2A in the read only memory 11. More specifically, referring to Table 1, a storing state for representing a note being produced is represented by the logic one and a storing state for representing a note being not produced is represented by the logic zero. For each address, the first bit position is allotted to maracas, the second bit position is allotted to cymbal, the third bit position is high-bongo, the fourth bit position is allotted to low-bongo, the fifth bit position is allotted to high-hat cymbals, the sixth bit position is allotted to snare drum, and the seventh bit position is allotted to bass drum, so that various kinds of musical instruments are determined by the respective bit positions, while the eighth bit position is left as a vacant address. In the first bit position of the read only memory 11, for example, the logic one is written in the addresses serving as a head address, i.e. the address No. 0, and in every third address among the addresses of the unit number, i.e. forty-eight addresses for storing rhythm information concerning samba, whereby rhythm information concerning samba represented by the notes being produced by a maracas is written in the read only memory 11. Similarly, the storing states of the logic one for the rhythm information of the notes being produced by cymbal, high-bongo and low-bongo are written in the corresponding addresses of the second, third and fourth bit positions in the read only memory 11, as shown in Table 1. The rhythm information concerning slow rock by three kinds of musical instruments, i.e. high-hat cymbals, snare drum and bass drum as shown in FIG. 2B is written in the read only memory by loading the logic one in the corresponding addresses in the storing region for slow rock, i.e. the addresses Nos. 48 to 95 at the fifth, sixth and seventh bit positions, as shown in Table 2.
In operation, for the purpose of generating a rhythm of samba based on the rhythm information preloaded in the above described read only memory 11, first the samba rhythm is selected by means of the rhythm selection circuit 13. Accordingly, the rhythm selection circuit 13 generates the address data for addressing the head address, i.e. the address No. 0 in the read only memory 11 where the rhythm information concerning samba is stored, which address data is applied to the address counter 12 for the purpose of initial setting. If and when the performer depresses the start stop command switch 141, the toggle type flip-flop 142 provides the high level signal. The rise of the high level signal thus obtained is differentiated by the differentiation circuit 143, thereby to provide the rise differentiated output, which is applied through the OR gate 144 to the address counter 12 as an initial setting signal, i.e. a head address command signal. The output of the toggle type flip-flop 142 is also applied to the clock signal generator 151 as an oscillation command signal. Accordingly, the clock generator 151 is enabled to generate reference clock signals of a predetermined cycle. The clock signals thus obtained are applied to the address counter 12 as an address step signal and also applied to the frequency divider 152 and further applied to the AND gates 161 to 167 at one input of each of the gates. Each time the address counter 12 receives the clock signal, a step operation is effected on a one by one address basis from the head address as selected by the rhythm selection circuit 13, whereby the rhythm information of the data as stored in the corresponding addresses of the read only memory 11 is read out. Assuming that the address counter 12 addresses the address No. 0 of the read only memory 11, for example, the logic one in the address No. 0 in the first bit position of the read only memory is read out through the AND gate 161 and is applied to the tone generator 171 to generate a sound signal of maracas and the logic one of the same address in the third bit position is read out through the AND gate 163 and is applied to the tone generator 173 to produce a sound signal of high-bongo, with the result that these sound signals are mixed and amplified by the amplifier 182 and a mixed sound is produced from the speaker 183. As the address counter 12 addresses in succession the first and second addresses, no sound is produced. If and when the address counter 12 addresses the address No. 3, a sound signal is generated by the tone generator 171 corresponding to the maracas. Thus, the address counter 12 makes a stepping operation in succession responsive to the reference clock signal obtainable from the clock generator 151, whereby the rhythm information of the data preloaded in the respective addresses is read out to control the tone generators, so that a mixed sound is produced. If and when the address counter 12 reaches the step value of the final address, i.e. the address No. 47 storing the rhythm information concerning samba, then the frequency divider 152 is responsive to the following clock signal to provide the frequency divided output obtainable as a result of frequency division of the reference clock signals by the frequency division rate of 1/48. The frequency divided output is applied through the OR gate 144 to the address counter 12 as a repeat command signal, for commanding return to the head address for storing the rhythm information concerning samba selected by the rhythm selection circuit 13 for the purpose of repetition of the above described operation. The above described operation is thus repeated until the start stop command switch 141 is again depressed, thereby to provide a stop signal to the toggle type flip-flop 142.
If and when the rhythm selection circuit 13 selects the rhythm of slow rock, the rhythm selection circuit 13 provides the address data addressing the head address for storing the rhythm information concerning slow rock i.e. the address No. 48, to the address counter 12. As a result, each time the address counter 12 is supplied with the reference clock signal, the addresses are in succession designated from the address No. 48, and the frequency divider 152 is responsive to the clock pulse signal obtainable following the addressing of the address No. 95 to provide the frequency divided output, thereby to repeat the addressing operation starting from the address No. 48. Although various other kinds of rhythm patterns are stored in the other addresses of the read only memory 11, further description thereof will be omitted.
The above described scheme, however, involves various disadvantages. More specifically, since the above described scheme is adapted such that the rhythm information is stored in the corresponding addresses of the read only memory and is read in synchronism with the reference clock signal being generated, the logic zero need to be written in the addresses where no sound is produced, which increases a required storage capacity of the read only memory, which in turn increases the cost. This problem is aggravated by an increase of the number of kinds of the rhythm patterns, in view of a corresponding increase of the storage capacity and the cost.